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1-24 avs technology inc. 4110 clipper ct., fremont ca94538 tel: (510) 353-0848 fax: (510) 353-0856 january 4, 2001 features ? fully ccir 624 performance compliance ntsc and pal (b,d,g,h,i,m and n) video encoder ? composite, s-video, component y/cb/cr (sony, matsushita, and smpte) or rgb output. ? triple 10-bit digital to analog converter. ? accepts 27 mhz multiplexed 8-bit digital video inputs. ? master or slave 4-field ntsc or 8-field pal video timing generation. ? ccir 656 eav sync extraction. ? automatic ntsc or pal timing detection in slave mode operation. ? automatic or user programmable chroma filter selection. ? macrovision anti-tapping rev 7.01 support in AV3168 only. ? closed caption support. ? contrast and brightness control. clock generation ? 3 outputs for 27 mhz video clock, 16.934, 18.432 and 36.864 mhz audio clock, and 40.5, 54.0, 67.5 and 81.0 mhz general purpose clocks. ? requires a single 27 mhz crystal. general ? cvbs and s-video dac power down con- trols. ? i 2 c compatible serial control bus. ? single +5 volt power supply. application ? digital video disk (dvd) ? digital set-top box ? pc video, multimedia ordering information AV3168/69-cl 44-pin plcc video tim'ng gen f sc lpf lpf off set z -n g g pd<7:0> cvbs, cr, b hsyn vsyn sda scl i c serial i/f rst color space conv. ack gck pll macrovision anti-tappin g y, y, r c, cb, g ck27 gout0 gout1 2 avs technology video encoder AV3168/69
AV3168/69 2-24 january 4, 2001 description the AV3168 is a mixed signal cmos monolithic device. it comprise with a pal and ntsc video encoder, color space converter and clock generator, the clock generator outputs a video, an audio and a programmable general purpose clock. this ic implemented macrovision anti-tapping 7.01, intended for dvd and settop box applications. the video encoder converts ccir 601 8-bit multiplexed digital video into rgb, component ycbcr, encoded ntsc or pal (bdghimn) signals. it contains three 10-bit dacs to support simultaneous s-video and composite video; or component video display. brightness and contrast control are also provided. the clock generator outputs three clocks for video, audio and system to simplify the system configuration and maintain a/v synchronization. pd<7:0> gck ck27 hsyn vsyn ack mpeg clock 27 mhz video clock 8-bit video bus horizontal s y nch vertical s y nch 384 times audio clock i c bus 2 i s bus xck dvd a/v decoder AV3168 audio dac 2 typical application connection
AV3168/69 3-24 january 4, 2001 video performance item specification 1 attenuation of luminance signal 0 - 5 mhz +/- 0.1 db 6 mhz > 3db 9 mhz > 35 db 2 attenuation of ntsc color difference signal 0.4 mhz < 1db 1 mhz 5 db 2 mhz > 25 db 3 attenuation of pal color difference sig- nal 1.3 mhz < 2db 3.6 mhz > 20db 4 attenuation of component color differ- ence signal 2 mhz < 3 db 5 mhz > 38 db 5 luma snr > 82 db 6 chroma snr am > 64 db pm > 60 db 7 differential gain < 0.5% 8 differential phase < 1 degree 9 y/c delay +/- 2 nsec. 10 y/c gain inequality +/- 2% 11 y/c intermodulation < 0.7 ire 12 sch < 4 degree
5 mhz lpf 2 4 pedestal modulation & gain f sc gen d/a 10 10 y c cvbs d/a 39 36 42 cpnt 43 pden video timin g generation vsyn mstr 68 pd<7:0> demux y cb cr 70 69 cvbs, b, cr y, r, y hsyn AV3168 eav 10 d/a 36 c, g, cb contrast color space conv. r, cb g,y b, cr mux sda scl i c serial i/f 2 macrovision 70 69 clock ck27 ack gck xout xin gout0 gout1 68 rst anti-tappin g close caption k[1:0] fsel[1:0] cont brtn fmt cmod[1:0] ccc palmn mono gen. 69 AV3168 detailed block diagram figure 1
AV3168/69 5-24 january 4, 2001 pin descriptions vref vss vss gout0 gout1 xout xin mstr vss vdd rst gck vss ck27 vdd pd0 pd1 pd2 pd3 pd4 pd5 vss pden cpnt vss ack scl sda vdd hsyn vsyn pd7 pd6 iref comp bias vdda cvbs vss c vdda y vss vdda 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29
AV3168/69 6-24 january 4, 2001 pin descriptions pin name pin # type description digital video input pd<7 -0> 11-16 18-19 i multiplexed cb, y, and cr digital video input bus. hsyn 21 i/o in slave mode (mstr pin is low) horizontal synch input. in master mode (mstr pin is high) horizontal synch output. vsyn 20 i/o in slave mode (mstr pin is low) vertical sync input. in master mode vertical sync output. video control signals mstr 3 i master mode; if this pin is high, the chip outputs horizontal and vertical sync signals. otherwise it receives both horizontal and vertical sync signals. cpnt 27 i select either component or composite video output. 0: simultaneous composite and s-video output. 1: component video output either rgb or ycbcr determined by the register cr0[5:4]. pden 28 1 pedestal enable pins. when this pin is high 7.5 ire is added for the ntsc composite analog output. video analog output, reference and compensation cvbs 35 o analog video output determined by the state of cpnt pin and cr0[5:4] cpnt cr0[5] cr0 [4] --- 0 ---- x ------ x: --- composite video output --- 1 ----- x ------ 0: --- cr output in ycbcr component mode --- 1 ---0 0 ------ x: --- 1111111111- : : --- 1 ------ 1 ------ 1: ---- blue color output in rgb mode y 31 o analog video output determined by the state of cpnt pin and cr0[5:4] cpnt cr0[5] cr0 [4] --- 0 ----- x ----- x: --- s-video y output. --i 1 ------ x ---- - 0: --- y output in ycbcr component mode --- 1 ---0 0 ------ x: -- 1111111111- : : - i 1 ----- 1 --- -- 1: - - r color output in rgb mode
AV3168/69 7-24 january 4, 2001 c 33 o analog video output determined by the state of cpnt pin and cr0[5:4] cpnt cr0[5] cr0 [4] --- 0 ------ x ------ x: -- s-video c output. ---- 1 ------ x ----- 0: --- cb output in ycbcr component mode --1 1 ------ 0 ---- x: 1111111- : : --1 1 ------ 1 ------ 1: -- green color output in rgb mode vref 40 i/o voltage reference. it has an internal voltage reference circuit, but may be overridden by an external voltage reference input. a 0.1 uf ceramic capacitor is required between this pin and gnd. iref 39 i a resistor should be connected between this pin and gnd to control the dac output current. the recommended value is 198 (382) ohm 1% metal film resistor for double (single) end 75 ohm termination. comp 38 i compensation capacitor for the dac internal reference amplifier. a 0.1 uf ceramic capacitor is required between this pin and vdda. bias 37 i/o dac bias voltage. a 0.1 uf ceramic capacitor must be used to de- couple this pin to vdda. serialcontrl bus scl 24 i serial bus clock sda 23 i/0 serial bus address and data input and output pin. open drain output. clock signals gck 7 o general purpose clock. clock frequency is determined by the state of gout[1:0] when rst pin is low. 00 : 40.5 mhz clock output. 0 1: 54.0 mhz clock output. 1 0: 67.5 mhz clock output. 1 1: 81.0 mhz ck27 9 o 27 mhz clock output pin. ack 25 i/o 384*fs audio clock output pin. controlled by cr2[1:0] 0 0: 384 * 48.0 khz (18.432mhz) clock output. 0 1: 384 * 44.1 khz (16.934mhz) clock output. 1 0. 384 * 96.0 khz (36.864mhz) clock output. 1 1: 384 * 88.2 khz (33.868mhz) clock output. pin descriptions (continued) pin name pin # type description
AV3168/69 8-24 january 4, 2001 xin 2 i 27 mhz oscillator input xout 1 o 27 mhz oscillator output miscellaneous signals rst 6 i active low chip reset input. chip is in the power down mode when the rst is low. gout1 44 i/o dual function pin. gck frequency select pin when rst is low. general purpose output pin when rst is high gout0 43 i/o dual function pin. gck frequency select pin when rst is low. general purpose output pin when rst is high power and ground vdd 10, 22, 5 +5v digital power supply. vss 8, 17, 26, 30, 34, 41, 42, 4 gnd digital ground vdda 29, 32, 36. +5v analog video power supply. pin descriptions (continued) pin name pin # type description
AV3168/69 9-24 january 4, 2001 video timing generation the video encoder can operate as a master or a slave in the timing generation. in the master mode, the video encoder outputs sync signals. in the slave mode, the internal timing is lock to the external sync signals. master mode if the mstr pin is high, the video encoder operates in the master mode. it uses the internal counters to generate the video timing and outputs hsyn and vsyn. the hsyns are asserted for 64 pixel times. the negative transition of the hsyns occur in the cb slot. the vsyns are asserted for 3 line times for ntsc and 2.5 for pal. the co-incident negative transitions of hsyn and vsyn indicate the beginning of an odd field. the negative transition of the vsyn while the hsyn is high indicates the beginning of an even field. slave mode in the slave mode operation, the decoder automatically detects the input format and locks the internal timing counters to the external synchronization signals. it support 2 types of synch inputs: (a) hsyn / vsync, or (b) ccir656 eav data. if eav is present, the video encoder synchronized to the eav packets according to ccir656 specifications to generate the video timing. hsyn and vsyn signals are ignored. if eav is not present, the video encoder uses the signals presented on hsyn and vsyn for line and field counter increment. if register cr0[3] is low the encoder assumes the negative transition of the hsyn should be co-incited with the cb0 datum. if cr0[3] is high it assume the transition co-incited with y0 datum. vsyn vsyn blanked 273 - 280 524 ntsc vertical interval timing 10 - 20 field one field two blanked 5251234 56789 262 263 264 265 266 267 268 269 270 271 272
AV3168/69 10-24 january 4, 2001 vsyn vsyn 7 - 20 320 - 333 pal vertical interval timing vsyn vsyn field 2 &6 field 3 & 7 field 4 & 8 blanked blanked blanked blanked 621 622 623 624 625 1 2 3 4 5 6 309 310 311 312 313 314 315 316 317 318 319 7 - 20 621 622 623 624 625 1 2 3 4 5 6 320 - 333 309 310 311 312 313 314 315 316 317 318 319 field 1 & 5
AV3168/69 11-24 january 4, 2001 luminance processing the luminance, y, are interpolated to 27 mhz sampling rate through a multi-tap linear poly-phase filter. the filter frequency response is flat from 0 to 5 mhz. contrast and brightness control are provided for minor adjustment only. . luminance filter contrast control item creg1<1:0> contrast 1 00 normal 2 01 less contrast 3 10 least contrast 4 11 high contrast brightness control item creg1<3:2> contrast 1 00 normal 2 01 modest brightness 3 10 high brightness 4 11 less brightness 0 2 4 6 8 10 12 -50 -40 -30 -20 -10 0 fre q uenc y ( mhz ) attenuation (db) luminance filter frequency response
AV3168/69 12-24 january 4, 2001 chrominance processing the cb and cr signals are filtered and interpolated to 27 mhz. the filter has 3 bandwidth: 0.675, 1.3 or 2 mhz. the filter bandwidth can be either auto select or user select via control register creg<7:6>. chrominance filter chroma filter bandwidth control item creg2<7:6> chroma bandwidth 100auto-select 2 01 0.675 mhz 3 10 1.375 mhz. 4 11 2.0 mhz 0 1 2 3 4 5 6 -50 -40 -30 -20 -10 0 fre q uenc y ( mhz ) attenuation (db) chrominance filter frequency response ntsc pal component
AV3168/69 13-24 january 4, 2001 clock frequency control the system clock, gck, output frequency is determined by the state of two general purpose output pins (gout0 and gout1) while the rst pin is low. the output frequencies are. the ack outputs 384 times 40.5, 48 or 96 khz audio clock. the clock frequency is selected via control register. cr2 <1:0> . system clock item gout<1:0> frequency (mhz) 1 00 40.5 2 01 54.0 3 10 67.5 4 11 81.0 audio clock item cr2<1:0> audio sampling frequency (khz) clock frequency (mhz) 1 00 48.0 18.432 2 01 44.1 16.934 3 10 96.0 36.864 4 11 88.2 33.869
AV3168/69 14-24 january 4, 2001 control and closed caption register description the AV3168 contains three 8-bit registers for timing generation, luma and chroma processing control, clock generation and power management. additionally it contains 4 closed caption data registers. these registers are programmed via the 7-bit address i 2 c bus. i 2 c address = 0x65. (i2c bus address = 0x64 for av3169 ). the protocol is 7- bit chip address followed by 8- bit register address and 8-bit register data. control register 0, cr0 (address: 0x0, default value: 0x00) item register bits mnemonic #bits description 1cr0 [ 7:6 ] fsel [ 1:0 ] 2 chroma filter selection 00: automatic bandwidth assi g nment based on the output format selection ( default ) 01: 0.675 mhz bandwidth 10: 1.36 mhz bandwidth 11: 2 mhz bandwidth 2cr0 [ 5:4 ] cmod [ 1:0 ] 2 component output selection. valid onl y if pin 27 cpnt pin is 1. 00: son y betacam ( default ) 01: mashushita m-ii 10: smpte 11: rgb 3cr0 [ 3 ] sdly 1 input hs y n ne g ative transition position 0: the ne g ative hsync transition coincided with cb 0 datum ( default ) 1: the ne g ative hsync transition co-incited with y 0 datum. 4cr0 [ 2 ] sch 1 subcarrier horizontal s y nc phase control ( sch ) 0: subcarrier reset ever y 4 fields for ntsc and ever y 8 field for pal ( default ) , sch =0 accordin g ccir 624 spec. 1: subcarrier free runnin g . 5cr0 [ 1 ] palmn 1 enable south american palm and paln 0: non-south american mode, pal ( bdghi ) , or ntsc ( default ) . 1: south american mode ( pal-m, pal-n ) 6cr0 [ 0 ] fmt0 1 used in master mode onl y to select either 525 or 625 line s y stem timin g . 0: 525-line m s y stem ( default ) 1: 626-line s y stem.
AV3168/69 15-24 january 4, 2001 control register 1, cr1 (address: 0x01, default value: 0x00) item register bits mnemonic #bits description 1 cr1[7] vbioff 1 vertical blanking interval disable. 1: vertical interval (vbi) is not blanked 0: vbi blanked (default) for m system line 1-21, 262-284, 525 are blanked. for 625 line system line 1-22, 311-335, 624 - 625 are blanked. 2 cr1[6:5] ccc 2 close caption enable 00: disable closed caption data (default) 10: enable closed caption data on odd field only. 01: enable closed caption data on even field only. 11: enable closed caption data on all fields 3 cr1[4] ydly 1 luma delay control 0: luma output not delayed (default) 1: luma output delayed by 74ns 4 cr1[3:2] bgt 2 brightness control 00: brightness control off (default) 01: moderate brightness gain 10: most brightness gain 11: least brightness gain 5 cr1[1:0] con 2 contrast control 00: contrast control off (default) 01: 15/16 * luma gain 10: 14/16 * luma gain 11: 17/16 * luma gain control register 2, cr2 (address: 0x02, default value: 0x00) item register bits mnemonic #bits description 1 cr2[7] bw 1 monochrome display 0: color display (default) 1: monochrome display 2 cr2[6] pwdcv 1 composite dac power down control. 0: enable cvbs dac (default) 1: power down cvbs dac 3 cr2[5] pwdyc 1 s-video dacs power down control. 0: s-video dac on (default) 1: s-video dac power down
AV3168/69 16-24 january 4, 2001 4 cr2[4] gouten 1 general purpose register gout<1:0> output enable. 0: pin 44 and 43 in high impedance state. 1: gout<1:0> are output to pin 44 and 43. 5 cr2[3:2] gout[1:0] 2 general purpose output registers. these regis- ters connected to pin 44 and 43 respectively. 6 cr2[1:0] k[1:0] 2 audio clock, ack, output frequency select 00: 48 * 384 khz 01: 44.1 * 384 khz 10: 96.0 * 384 khz 11: 88.2 * 384 khz extended closed caption register 0 (address: 0x03, default value: 0x00) register mnemonic #bits description ecc[15:8] ecc[15:8] 8 extended closed caption data (upper byte) extended closed caption register 1 (address: 0x04, default value: 0x00) register mnemonic #bits description ecc[7:0] ecc[7:0] 8 extended closed caption data (lower byte) closed caption register 0 (address: 0x05, default value: 0x00) register mnemonic #bits description cc[15:8] cc[15:8] 8 closed caption data (upper byte) closed caption register 1 (address: 0x06, default value: 0x00) register mnemonic #bits description cc[7:0] cc[7:0] 8 closed caption data (lower byte) control register 2, cr2 (address: 0x02, default value: 0x00) item register bits mnemonic #bits description
r/w ack a7 a0 d0 ack d7 ack start stop ca6 ca0 11 1 1 chip adrress: ca<6:0> = 65h register address: a<7:0> = 00h data: d<7:0> = 30h sda scl i 2 c bus control register write example: r/w ack a7 a0 d0 ack d7 ack start stop ca6 ca0 11 1 1 chip adrress: ca<6:0> = 65h register address: a<7:0> = 00h data: d<7:0> = 30h sda scl i 2 c bus control register write example: r/w ack a7 a0 d0 ack d7 ack start stop ca6 ca0 11 1 1 chip adrress: ca<6:0> = 65h re g ister address: a<7:0> = 00h data: d<7:0> = 30h sda scl i 2 c bus control re g ister write example:
AV3168/69 18-24 january 4, 2001 application circuit reconstruction filter (vlpf) for the double end 75 ohm termination AV3168 47 uf ferrite-bead vdd 5 10 22 vdda +5v connector vref iref 196 ohm comp 75 ohm y c vlpf video c1 c2 c3 c4 c5 47uf c6 c7 c8 c9 de-cou p lin g and analo g connections 29,32,36 bias csvb xin xout 12~22pf 12~22pf 27.0000 mhz 35 31 33 c1 -c10 are 0.1 uf capacitors gout1 gout0 +5 v gck selection c10 +5 v sdl sda i c 2 100 ohm 1.5 k video output tv 75 ohm 22 pf 180 pf 180 pf 75 ohm 1.8 uh
AV3168/69 19-24 january 4, 2001 digital video input port timing diagram . figure 1: pixel bus . figure 2: horizontal sync and vertical sync signals figure 3: i 2 c serial port timing tck 27 l pd<7:0> tpd su tpd hd ck27 tck 27 h hsyn tsy su tsy hd ck27 vsyn scl sda p s tbuf thd;sta tlow thigh tf tr thd;dat tsu;dat sr tsu;sta p tsu;sto
AV3168/69 20-24 january 4, 2001 absolute maximum ratings notes: 1. absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. applied voltage must be current limited to specified range, and measured with respect to vss. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current, flowing into the device. symbol characteristics min max units v dd power supply voltage (measured to gnd) -0.5 +7.0 v v i digital input applied voltage 2 gnd-0.5 v a i digital input forced current 3,4 -100 100 ma v o digital output applied voltage 2 gnd-0.5 v dd +0.5 v a o digital output forced current 3,4 -100 100 ma tdsc digital short circuit duration (single output high state to vss) 1sec ta sc analog short circuit duration (single output to vss1) infinite sec t a ambient operating temperature range -25 +125 o c tstg storage temperature range -65 +150 o c t j junction temperature (plastic package) -65 +150 o c tsol lead soldering temperature (10 sec., 1/4 from pin) 300 o c tvsol vapor phase soldering (1 minute) 220 o c t stor storage temperature -65 +150 o c
AV3168/69 21-24 january 4, 2001 recommended operating conditions electrical chracteristics symbol characteristics min typical max units v dd power supply voltage 4.35 5 5.25 v v ref reference voltage 1.235 v iref reference current 3.15 ma r l analog output load 37.5 70 t a ambient operating temperature range 0 70 o c symbol characteristics min typ max units supply i dd total power supply current, analog + digital 130 tbd ma i ddq total power supply current, dac power down 37 tbd ma digital characteristics v ih digital input voltage, logic high, ttl compatible inputs. 2.0 v dd v v il digital input voltage, logic low, ttl compatible inputs v ss 0.8 v i ih digital input current, logic high, (v in =4.0v) 10 a i il digital input current, logic low, (v in =0.4v) -10 a c in digital input capacitance (f=1mhz, v in =2.4v) 7 pf v oh digital output voltage, logic high, cmos compatible outputs (i oh = -1ma) 3.7 v dd v v ol digital output voltage, logic low, cmos compatible outputs (i ol =4.0 ma) v ss 0.4 v i ozh hi-z leakage current, high, v dd =max, v in =v dd) 10 a i ozl hi-z leakage current, low, v dd =max, v in =v ss) -10 a c i digital input capacitance (t a =25 o c, f=1mhz) 8 pf c o digital output capacitance (t a =25 o c, f=1mhz) 10 pf video clock and oscillator signal fx crystal oscillator input frequency -30 ppm 27.0000 +30 ppm mhz f27 27 mhz clock,ck27, frequency 27.0000 mhz t ck 27 h ck27 pulse width, high 10 18.5 ns w m m m m
AV3168/69 22-24 january 4, 2001 t ck 27 l ck27 pulse width, low 14.5 18.5 ns video bus master mode timing t pd su digital pixel data p<7:0> input setup time 8 ns t pd hd digital pixel data p<7:0> input hold time 3 ns t sy su hsyn and vsyn output setup time 10 ns t sy hd hsyn and vsyn output setup time 6 ns video bus slave mode timing t pd su digital pixel data p<7:0> input setup time 8 ns t pd hd digital pixel data p<7:0> input hold time 3 ns t sy su hsyn and vsyn input setup time 8 ns t sy hd hsyn and vsyn input setup time 3 ns miscellaneous digital signals t pwd rst , active low reset time 1 s serial port timing fsc scl clock frequency 100 khz tsu;sta start condition set up time 4.7 us thd;sta start condition hold time 4.0 us tsu;sto stop condition set up time 4.0 us t low scl low time 4.7 us t high scl high time 4.0 us tr scl & sda rise time 1.0 us tf scl & sda fall time 0.3 us tsu; dat data set-up time 250 ns thd; dat data hold time 0 ns tvd; dat scl low to data out valid 3.4 us tbuf bus free time 4.7 us analog video (dac) outputs res dac resolution 10 bits psrr power supply rejection ratio (full scale out- put) comp=0.1 f, f=dc to 1 mhz, v rip = 100 mv p-p.) tbd db v ro voltage reference (vref) output 1.112 1.235 1.359 v z r voltage reference output impedance 10 k k dac dac gain factor 10.31 10.85 11.39 symbol characteristics min typ max units m m w
AV3168/69 23-24 january 4, 2001 k imbac k dac imbalance between dacs -1 +1 % i ref dac reference current (i ref =nominal) 3.15 ma r ref reference resistor (v ro =nominal) 196 v blank blanking level output voltage (ntsc and pal modes) 0.300 v v oc video output compliance voltage -0.3 1.6 v c out video output capacitance (i out =0 ma, f=1mhz) 20 pf r l total output load resistance 37.5 t dov analog output delay 20 ns symbol characteristics min typ max units w w
AV3168/69 24-24 january 4, 2001 packaging information dimensions max norm min unit max norm min unit a2.15 mm. d 0.53 0.406 0.33 mm. b1.27mm. e 16.00 15.748 mm. c 1.22 1.07 mm. f 0.51 mm. d 0.81 0.736 mm. g 3.04 2.565 mm. a 17.65 17.526 mm. h 4.57 4.368 mm. b 16.66 16.612 mm. 1 6 45 17 18 7 28 29 39 40 44 a b c d a b d e f g h 44-pin plastic leaded chip carrier (plcc)

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